Integrated circuits incorporating memory devices can fail before leaving the manufacturing facility as well as in the field. However, any failure of a memory device presents an unacceptable situation to a user or vendor of a product with a memory device.
A defect in insulation can lead to such failures. For example, in a typical static random access memory cell, two bit lines are connected to each memory cell by pass gate transistors, which are turned on by a word line. The bit lines are usually metallized strips; they must be insulated from each other and from other areas of the memory cell. Oxide layers usually provide such electrical insulation. Unfortunately, defects can develop in the insulating oxide layer between side-by-side metallized strips and also between upper and lower conductive layers. These defects can be the result of a thinning of the oxide and can effectively reduce the distance between conductive layers. Resistive shorts between metallized strips can also occur. Insulation layers between different levels of conductors, such as poly one, poly two and metal can similarly fail and result in failure of the memory device.
It is desirable to perform rapid testing to expose defects in a device before shipping a product with a memory to a vendor or user. Current testing methods include applying voltages to a memory device and writing test patterns. This may not, however, expose all defects in the oxide layers between adjacent bit lines and other conductors. For example, if adjacent bit lines or conductors of a memory device are placed in the same logic state and a resistive short or other defect exists between those adjacent bit lines, then the defect will not be found because there is no stress between them. A weakened dielectric will not be stressed by such a test and may break down after several hours of use in the field. The defect will therefore remain undetected. Thus, there is an unmet need in the art to be able to detect defects associated with bit line performance of a memory device.